1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor optical device, and more specifically to a method for manufacturing a semiconductor optical device having an electrode on the top of a waveguide ridge.
2. Description of the Related Art
In recent years, as a semiconductor laser that can emit light from a blue region to a violet region required in high-density optical disks, a nitride semiconductor laser using a III-V nitride compound semiconductor, such as AlGaInN, has been actively studied and developed, and has been already put in practical use.
Such a blue-violet laser diode (hereafter, a laser diode will be abbreviated as an LD) is formed by growing the crystals of a compound semiconductor on a GaN substrate.
Typical compound semiconductors include III-V compound semiconductors wherein a group III element is combined with a group V element, and by combining a plurality of group III atoms and group V atoms, mixed-crystal compound semiconductors having various composition ratios can be obtained. The examples of compound semiconductors used in blue-violet LDs include GaN, GaPN, GaNAs, InGaN, and AlGaN.
An LD of a waveguide ridge type is normally provided with an electrode layer on the top of the waveguide ridge. The electrode layer is connected to a contact layer, which is the uppermost layer of the waveguide ridge, through an opening formed on the top if the waveguide ridge in an insulating film that coats the waveguide ridge. The insulating film having the opening is formed by a liftoff method using a resist mask used when the waveguide ridge is formed. Since the resist mask adhered to the contact layer for this purpose is depressed along the surface of the contact layer in the joining portion with the contact layer, a part of the insulating film that coats the waveguide ridge along this dent is left even after liftoff, and only the remaining insulating film coats the surface of the contact layer, resulting in that the contact area between the electrode layer and the contact layer is smaller than the entire surface area of the contact layer.
Since the materials for contact layers used in conventional red LDs, such as GaAs, have relatively low contact resistances, decrease in the contact area caused by the liftoff method did not significantly increase the contact resistance, and did not significantly effect the elevation of the operating voltage of the LD.
However, in the case of a blue-violet LD, since the material used in the contact layer is GaN or the like, and the contact resistance of the material is relatively high, decrease in the contact area between the electrode and the contact layer elevated the contact resistance between the electrode and the contact layer, resulting in the elevation of the operating voltage of the blue-violet LD.
Known examples of LD manufacturing methods to prevent decrease in the contact area between an electrode and a contact layer are as follows:
In the case of forming a nitride semiconductor laser element, a p-type electrode layer 112 composed of palladium/molybdenum/gold is first formed on a p-type contact layer 111 of a wafer containing a plurality of semiconductor layers. Next, a stripe-shaped resist mask (not shown) is formed on the p-type electrode layer 112, and ridge stripes 114 are formed using RIE (reactive ion etching). Specifically, the p-type electrode layer 112 is formed by etching using Ar gas, and ridge stripes 114 are formed by etching the p-type contact layer 111 and to the middle of the p-type clad layer 110, or by etching to the middle of the p-type guide layer 109 using a mixed gas of Ar, Cl2 and SiCl4. Furthermore, an insulating film 115 (Zr oxides consisting mainly of ZrO2) having a thickness of 0.5 μm is formed so as to coat the upper surface of the wafer leaving the resist of the ridge stripes 114. Thereafter, the resist is removed to expose the upper sides of the ridge stripes 114. Furthermore, a p-type pad electrode 116 composed of molybdenum and gold is formed so as to coat the p-type electrode layer 112 and at least the insulating films 115 in the vicinity of the both sides thereof. (For example, refer to National Publication of International Patent Application No. JP WO 2003/085790 A1, p. 9, 1. 42-50, and FIG. 1.)
In another known example discloses a self-aligning method for manufacturing a ridge waveguide semiconductor LD including a step for laminating two different photo-resist layers. The manufacturing method is as follows:
The lower photo-resist layer reacts only with the light having a wavelength of shorter than 300 nm; and the upper photo-resist layer reacts only with the light having a wavelength of longer than 300 nm. In a semiconductor laminated structure wherein a second coated waveguide 406 is formed and a cap layer 408 is formed thereon, the cap layer 408 and a part of the second coated waveguide layer 406 are removed to form a ridge structure 414 and a double channel 412. Furthermore, a second insulating film 416 is formed on the surface of the ridge structure 414 and the double channel 412. On the second insulating film 416, a lower-layer first photo-resist layer 420 and an upper-layer second photo-resist layer 422 are formed. The second photo-resist layer 422 is patterned to expose the first photo-resist layer 420 in the vicinity of the ridge structure 414. Next, to expose the second insulating film 416 on the ridge structure 414, an RIE process is carried out to the first photo-resist layer 420. Then, to remove the second insulating film 416 outside the ridge structure 414, an etching process including an RIE process is executed. Next, the remaining first photo-resist layer 420 and second photo-resist layer 422 are removed, and a first metal layer 424 is vapor-deposited as an electrode. (For example, refer to Japanese Patent Application Laid-Open No. 2000-22261, paragraph Nos. [0024] to [0034], and FIGS. 7 to 18.)
Further in another known example, the following method is disclosed: A ridge and a channel are formed by etching the contact layer by wet etching using an Al metal mask, and further performing wet etching using the contact layer as a mask while leaving the Al metal mask; and an insulating film is formed on the entire surface by plasma CVD, then, the Al pattern and the insulating film deposited thereon is removed by a lift off method. Next, using a normal lithography process, a resist pattern, wherein the p-side electrode portion is exposed, is formed, and an electrode material is vacuum-deposited using the resist pattern as the mask, and the resist pattern and the electrode material are removed by a liftoff method to form an electrode closely contacting the contact layer of the ridge. (For example, refer to Japanese Patent Application Laid-Open No. 2000-340880, paragraph Nos. [0025] to [0034], and FIG. 1.)
Further in another known example, the following method is disclosed: A first protecting film 61 is formed on the substantially entire surface of a contact layer 13, and a stripe-shaped third protecting film 63 is formed on the first protecting film 61. After etching the first protecting film 61 leaving the third protecting film 63, the third protecting film 63 is removed, and a stripe-shaped first protecting film 61 is formed. Then, by etching the p-side contact layer 13 and to the middle of the layer under the contact layer, for example, the p-side clad layer 12, to form a stripe-shaped waveguide. Next, an insulating second protecting film 62 is formed of a material different from the first protecting film 61 on the side of the stripe-shaped waveguide and the nitride semiconductor layer exposed by etching, the plane of the p-type clad layer 12 in the previous etching; only the first protecting film 61 is removed by a liftoff method; and a p-electrode electrically connected to a p-side contact layer 13 is formed on the second protecting film and the p-side contact layer 13. (For example, refer to Japanese Patent Application Laid-Open No. 2003-142769, paragraph Nos. [0020] to [0027], and FIG. 1.)
By these conventional methods, even if the contact area between the contact layer and the electrode layer of the waveguide ridge is secured, there were problems in stably manufacturing a device having all favorable characteristics, such as the step for simultaneously etching the metal film and the semiconductor layer under the metal film; the step for discontinue etching stably leaving a predetermined thickness of the underlying resist when two layers of resist were used; and the step performing liftoff when a metal film was used as the mask or a plurality of protective films were used. There were also problems of the lowering of process freedom or the like when a plurality of resists or protective films were used.
Therefore, in order to stably prevent the shrinkage of the contact area between the semiconductor layer and the electrode layer on the upper surface of the waveguide ridge, the following manufacturing process has been developed.
First, a waveguide ridge is formed by forming channels in a wafer formed by laminating semiconductor layers, and an SiO2 film is formed on the entire surface of the wafer. Then, a resist is applied onto the entire surface of the wafer to form a resist film so that the resist films in the channels are thicker than the resist film on the top of the waveguide ridge. Next, the resist is evenly removed from the surface of the resist film by dry etching, and the resist film on the top of the waveguide ridge is removed leaving the resist films in the channels to form a resist pattern to expose the top of the waveguide ridge. Then, the exposed SiO2 film is evenly etched from the surface using the resist pattern as the mask, and the SiO2 film formed on the top of the waveguide ridge is removed leaving SiO2 films formed on the sides and bottoms of the channels to surely form opening in the SiO2 film on the top of the waveguide ridge.
Next, after removing the resist pattern, a p-side electrode is formed on the top of the waveguide ridge.
As a heretofore known example for forming ridge stripes using a p-type ohmic electrode as a mask, there has been disclosed an example wherein a stripe-shaped metal layer (first layer: Ni/Au, second layer: Pt) is formed on the upper surface of a p-type contact layer composed of GaN, then, heat treatment (alloying) is performed to form a p-type ohmic electrode, and etching is performed until the p-type guide layer is exposed using Cl2 as an etching gas and using the p-type ohmic electrode as a mask. (For example, refer to Japanese Patent Application Laid-Open No. 2004-253545, paragraph Nos. [0035] to [0038], and FIG. 2.)
As another heretofore known example for forming a ridge, the following process has been disclosed. In the first step, a first protective film 61 composed of an oxide of Si on the substantially entire surface of the p-side contact layer 13, and a stripe-shaped third protective film 63 is formed on the first protective film 61. After etching the first protective film 61 leaving the third protective film 63, the third protective film 63 is removed to form the stripe-shaped first protective film 61. Then in the second step, etching is performed from the portion where the first protective film 61 has not been formed in the p-side contact layer 13 on which the first protective film 61 is formed to form a stripe shaped waveguide region corresponding to the protective film in the portion immediately below the first protective film 61. Next in the third step, using an insulating material that is a material different from the first protective film 61, a second protective film is formed on the sides of the stripe-shaped waveguide, the surface of the nitride semiconductor layer (p-side clad layer 12) exposed by etching, and the first protective film 61. After forming the second protective film 62, by removing the first protective film 61 by etching, only the second protective film formed on the first protective film 61 is removed, and the second protective film is continuously formed on the sides of the stripes and the surface of the p-side clad layer 12.
Although the etching treatment in the third step is not specifically limited, for example a method to perform dry etching using hydrofluoric acid is included. (For example, refer to Japanese Patent Application Laid-Open No. 2000-114664, paragraph Nos. [0018] to [0024], and FIG. 6.)
In the steps of conventional methods, that is, forming a waveguide ridge by forming channels in a wafer, coating the wafer with the SiO2 film, applying a resist onto the SiO2 film, forming a resist pattern wherein the top of the waveguide ridge is exposed leaving the resist film in the channels, and evenly etching the exposed SiO2 film from the surface, removing the SiO2 film formed on the top of the waveguide ridge leaving the SiO2 film formed on the sides and the bottoms of the channels to form an opening in the SiO2 film on the top of the waveguide ridge; when dry etching is performed to etch off the SiO2 film in the step for forming the opening in the SiO2 film on the top of the waveguide ridge, damages in the semiconductor layer coated by the SiO2 film might be caused by etching. For example, when the underlying layer of the SiO2 film was a p-type contact layer, it might be damaged by etching, and contact resistance might be elevated. Especially when the p-type contact layer was composed of a material containing GaN, there was a problem in that it was difficult to remove the material containing GaN by wet etching, and it was difficult to remove the damaged portion by wet etching.